Are you a Physical Design Engineer, searching for a job where you can enhance your experience in a reputed organization? If yes, then log on to wisdomjobs page to search for the various job opportunities available for you in some of the best organizations, who promise to give you a handsome pay. An experience in a Physical Design job will help you to carry out a lead role in block level activities such as floor plans, STA, abstract view generation, schematic-to-layout verifications, improving RTL and route flows. Based on your qualifications and experience you can search from the job list available to you on wisdomjobs. Apply to the job you think is the best for you and also read the Physical Design job interview questions and answers which are specially prepared for you, to help you pass the interview level easily.
Question 1. Why Metal Density Rules Are Important?
Answer :
Metal Density rules take care of metal over-etching and metal lift off issues encountered durinf manufacturing process.
Question 2. Why Power Stripes Routed In The Top Metal Layers?
Answer :
Power routes generally conduct a lot of current. In order to reduce effect of IR drop, we need to make these routes less resistive. Top metal layers are thicker and offer lesser resistance. This helps to reduce IR drop.
Question 3. Types Of Checks That Can Be Done In Prime Time ?
Answer :
Timing (setup, hold, transition), design constraints, nets, noise, clock skew and analysis coverage.
Question 4. How Do You Validate Your Floorplan And What Analysis You Do During Floorplan?
Answer :
Question 5. How Many Clocks You Had In Your Designs? How Did You Do Cts For The Same?
Answer :
I had 5 clocks in my designs, sys_clk, sys_rclk, uart_clk, g_clk and scan_clk, where sys_clk, g_clk and uart_clk logically exclusive to scan_clk.
Answer :
Metal Jumper and Antenna diode are two methods to resolve Antenna violations. But Metal Jumper is preferred approach as it does not need change to the Netlist and placement. This methodology works for antenna violations on all metal layers except for the top most layer. In this methodology, we will switch the small portion of routing to higher level metal close to the location of failing gate. This will make sure that accumulated charges on metal layer does not affect the gate as gate will not be connected to the charge carrying metal route until higher level metal is manufactured.
For example, lets say antenna violation is in M2. This means that M2 has enough area to accumulate large charge that induces high electron voltage to destroy the gate. To solve this problem, we cut a portion of M2 close to failing gate and move the routing to M3. This makes sure that when M2 is being manufactured, it does not get connected to gate. Connection happens only when M3 gets manufactured which is much later in time. By then charges on Metal M2 would have leaked away.
When metal jumper is not possible to implement (probably due to routing congestion or violation happening in top most layer) we try to fix it by inserting antenna diode closed to gate failing antenna. Antenna diode provide electrical path for safe conduction of accumulated charges to the substrate. Antenna diode is a reversed biased diode but acts like resistor during manufactured process (CMP) due to high temperature environment.
Question 7. How Do You Reduce Power Dissipation Using High Vt And Low Vt On Your Design?
Answer :
HVT cells have a larger delay but less leakage. +ve slack in a design is not useful as having only some paths working faster will not help overall design. We are good if the slack is 0. In such cases give up the slack by using HVT cells but gain on power dissipation.
LVT cells are very fast but very leaky. Limit the use of LVT cells to only those paths that have difficulty in closing time.
Question 8. What Is Electromigration And How To Fix It?
Answer :
Electromigration (EM) refer to the phenomenon of movement of metal atoms due to momentum transfer from conducting electrons to metal atoms. Current conduction over a period of time in a metal route causes opens or shorts due to EM effect. EM effect cannot be avoided.
In order to minimize its effect, we use wider wires so that even with EM effect wire stays wide enough to conduct over the lifetime of the IC.
Question 9. What Are The Various Statistics Available In Ir Drop Reports?
Answer :
Question 10. What Is The Importance Of Ir Drop Analysis?
Answer :
IR drop determines the level of voltage at the pins of standard cells. Value of acceptable IR drop will be decided at the start of the project and it is one of the factors used to determine the derate value.
If the value of IR drop is more than the acceptable value, it calls to change the derate value. Without this change, timing calculation becomes optimistic. For example setup slack calculated by the tool is less than the reality.
Question 11. In Which Field Are You Interested?
Answer :
Answer :
Refer here and browse for different low power techniques.
Question 13. Do You Know About Input Vector Controlled Method Of Leakage Reduction?
Answer :
Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.
Question 14. How Can You Reduce Dynamic Power?
Answer :
Question 15. What Are The Vectors Of Dynamic Power?
Answer :
Voltage and Current
Question 16. How Will You Do Power Planning?
Answer :
Refer here for power planning.
Question 17. If You Have Both Ir Drop And Congestion How Will You Fix It?
Answer :
Answer :
Answer :
Question 20. How Will You Decide Best Floor Plan?
Answer :
Refer here for floor planning.
Answer :
Question 22. How Will You Synthesize Clock Tree?
Answer :
Question 23. How Many Clocks Were There In This Project?
Answer :
Question 24. How Did You Handle All Those Clocks?
Answer :
Question 25. Are They Come From Separate External Resources Or Pll?
Answer :
Question 26. Why Buffers Are Used In Clock Tree?
Answer :
To balance skew (i.e. flop to flop delay)
Question 27. What Is Cross Talk?
Answer :
Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This affect is known as cros talk. Cross talk may lead setup or hold voilation.
Question 28. How Can You Avoid Cross Talk?
Answer :
Question 29. How Shielding Avoids Crosstalk Problem? What Exactly Happens There?
Answer :
Question 30. How Spacing Helps In Reducing Crosstalk Noise?
Answer :
width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less cross talk
Question 31. Why Double Spacing And Multiple Vias Are Used Related To Clock?
Answer :
Question 32. How Buffer Can Be Used In Victim To Avoid Crosstalk?
Answer :
Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to coupled signal from aggressor.
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