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  • 3 - 12 Years
  • Posted : above 1 month

Job Description:

Senior Verification Engineer System Verilog, OVM / UVM -Bangalore and Onsite 3 - 12YearsBangalorePosted On 30-11--0001 Functional Area IT - Software Functional Role IT Software - Other Experience 3 - 12Years Job Location Bangalore Senior Verification Engineer System Verilog, OVM / UVM Skillset Must Have Block and Top level verification know-how Verification Plan Development System Verilog/OVM or UVM Testbench Development VHDL/Verilog simulation and debug Scripting Nice to have HVL Specman is a plus End to End RTL Functional Verification Concepts Understanding of power aware architecture Experience Must have 3 12 Years Of Experience Performing feature extraction from a specification Coverage closure Experience of other HVLs (eg System Verilog) and methodologies (eg UVM) Nice to have Experience in Mobility, NFC or Multimedia Applications Job Description Responsibilities Develop Verification Plan and Verification Architecture Develop Tests and Testbench Implement Functional Coverage Points Achieve 100 PERCENT 25 Functional Coverage Develop Verification Plan Documentation and Capture Results of Execution Location Bangalore Notice Period Immediate Joining

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Consulting Services
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : As per Industry Standards
Deadline : 17th Nov 2019

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