• RTL Design Engineer - VHDL/Verilog Jobs in Bangalore,India

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  • 3 - 8 Years
  • Posted : above 1 month

Job Description:

a UNIX, shell scripting, PERL scripting

b Verilog, VHDL

c Hands on experience in waveform dump, analysis, RTL integration( Mandatory)

d Hands on experience on emulation debug and bring up (Zebu/Veloce) ( Mandatory)

e Good to have exposure to C/C++

Skill set

- 5+ years of RTL, - Verilog, System - Verilog, - VHDL experience Comfortable with Perl and C

- Experience with USB, microprocessor, SDIO/SD/eMMC at RTL Ievel will be plus

- Logic analyzer, PCB/hardware bring up and debug will be plus

- Protocol level RTL implementation knowledge on USB/OTG, PCIe, eMMC

- SDIO/SD, ARC or some microcontroller, SPI, DDR4 memory

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 17th Nov 2019

Key Skills:

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