• Noida, Greater Noida, Uttar Pradesh
  • Save Job
  • 0 - 3 Years
  • Posted : above 1 month

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology This is an entry level position in Solution Validation The primary role is to create tests that exercise the defined SVG Solutions like MDV and Functional Safety

Additional roles are to validate SVG-wide language interoperability like SV and LP, as well as, validate Design and Verification flows across SVG tools

A Bachelors degree in Electronics Engineering or Computers Science is required Candidates are expected to have a background in System Verilog RTL design and Verification Knowledge of UVM driven verification and Low-power verification of designs is a plus Scripting in PERL or Python, as well as, shell or Tcl Scripting is required

Good written and verbal skills are required for this role Candidates will have to work with multiple teams in multiple time zones

Were doing work that matters Help us solve what others cant

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Telecom, IT-Hardware/Networking
Functional Area : IT Software : Software Products & Services
Role : Software Engineer
Salary : 200000-400000 P/A
Deadline : 26th Oct 2019

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