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  • 3 - 6 Years
  • Posted : above 1 month

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology As a member of the Logic Design Team for Xtensa processors you will be responsible for the development of microprocessor cores, single and multi-processor sub-systems and their peripherals Under the supervision of a team lead, you will document micro-architecture specifications, design and implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other EDA scripts to meet timing, area and power goals You will also assist with developing testplans, writing functional diagnostics, debugging failures and analyzing coverage information You will work closely with the Design Verification and EDA teams

Required Skills and Experience

MS (or higher) in EE /Computer Engg with 3 years of relevant design experience
Excellent logic design demonstrated by successful ASIC or SoC implementations
Knowledge of computer architecture and pipelined designs is essential
Knowledge of Verilog and popular EDA simulation & implementation tools
Knowledge of scripting languages like Perl, Unix shell or similar languages
Excellent written and oral communication skills necessary
Good team player and interpersonal skills

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Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Telecom, IT-Hardware/Networking
Functional Area : IT Software : Software Products & Services
Role : Software Engineer
Salary : As per Industry Standards
Deadline : 23rd Nov 2019

Key Skills:

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