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Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology Highly proficient in RTL design using Verilog/System Verilog with experience in high speed DSP datapath designs as well as control FSMs for PPA optimizations
Deep knowledge in Synthesis, DFT and STA flows including lib generation for hard macros as well as good exposure to PNR handoffs and design fixes to meet timing
Experience of working in time domain signal processing blocks interfacing high speed mixed-signal blocks such as data converters, PLLs is highly desired
Good knowledge of high Speed Serdes PHYs such as USB, PCIe, Ethernet (10G/40G/100G/200G/400G etc) is preferred
Involved in delivery of complex DDR/Serdes IPs to customers and support
Closely working with analog teams for algorithm development and Silicon validation teams to bring-up Silicon as well as fine tune and debug performance issues at high speed
Good working knowledge SOCs involving DSPs / uC development for embedded systems
Proficient in Scripting languages such as Perl and working with Firmware team for development in C

Were doing work that matters Help us solve what others cant

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Telecom, IT-Hardware/Networking
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : As per Industry Standards
Deadline : 19th Nov 2019

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