• Overseas, International, Eu, Finland

Job Description:


Total Experience 5+ Years


- RTL verification of FPGAs

- Good knowledge of system Verilog/Verilog

- Good knowledge in Verification methodologies, preferably UVM

- Knowledge of scripting language preferably in Python and Perl

- Test environment in Python and Perl

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 28th Dec 2019

Key Skills:

Company Profile:

Not Mentioned

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