• United States Of America, Usa
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  • 0 - 3 Years
  • Posted : above 1 month

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology Job Description

This is an opportunity to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows The candidate will primarily be responsible for front-end coding, scripting and developing flows at all phases of the digital design and functional verification It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with the digital, analog and application teams Candidate should be willing to work full time in the San Jose office

Position Requirements

The ideal candidate will have a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status This includes but is not limited to

Digital microarchitecture definition and documentation
RTL logic design, debug and functional verification
IP integration and verification
Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus
Understanding of digital architecture trade-offs for power, performance, and area
Understanding of proper handling of multiple asynchronous clock domains and their crossings
Understanding of Lint checks and proper resolution of errors
Understanding synthesis timing constraints, static timing analysis and constraint development
Understanding of fundamental physical design flows and stages
Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow
Exhibit excellent communication skills and be self-motivated and well organized
Experience with FPGA and/or emulation platform is a plus
Firmware development of embedded micro-controller systems is a plus

Substantial experience with Verilog is required, as are excellent logic and debug skills Engineering expertise in mixed-signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly preferred

Were doing work that matters Help us solve what others cant

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Telecom, IT-Hardware/Networking
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : 200000-400000 P/A
Deadline : 14th Oct 2019

Key Skills:

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