• Noida, Greater Noida, Uttar Pradesh
  • Save Job
  • 6 - 9 Years
  • Posted : above 1 month

Job Description:

California, United States Design Engineer Experience 2 to 10 yrs Skills Required Job Summary RTL design experience for 6 years Architecture of the chip IC Design Clock, Clock gating, Reset expertise Experience in PCIe Logical Phy, PIPE interface Familiarity with PCIe IOs like Avago/Semtek/Synopsys Tool expertise Spyglass-DFT,LP,TXV; CDC, Synthesis Scripting Perl, Tcl Work Scope Modifying the existing Intel PCIe controller stack design to integrate the Intel Custom Foundry VersaPHY serial I/Os Architecting & defining the clocking strategy for the controller to work with the VersaPHY IO speed changes Integrating the ICF VersaPHY serial I/Os to the PCIe controller via PIPE interface Coding up the initialization / reset sequence to bring the integrated controller/IO stack out of reset Getting the PCIe links trained up to Gen1/2/3 Debugging & fixing all issues related to these activities

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Consulting Services
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : 500000-1000000 P/A
Deadline : 10th Nov 2019

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