• China

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure

The candidate will have the opportunity to work on many varieties of challenging designs, ie low power and high speed design The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development

Position Requirements

Bachelor degree with 5 years of applicable experience, Master degree with 3 years of applicable experience in electrical engineering, microelectronics

Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues

Solid knowledge on Low Power Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM

Successful track records of taping out complex chips at various technology nodes Experience with advanced nodes at 16nm and below is preferred

Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl

Self-motivated, able to work as a team player, excellent verbal and written communication skills in English

Were doing work that matters Help us solve what others cant

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Telecom, IT-Hardware/Networking
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : 300000-600000 P/A
Deadline : 29th Oct 2019

Key Skills:

Company Profile:


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