VLSI Design FPGA Technology VLSI Design

What is VLSI Design FPGA Technology?

FPGA – Introduction

The abbreviation of FPGA is “Field Programmable Gate Array”. It comprises ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are obtainable for users or designers to do functions simply. A classic model FPGA chip is revealed in the given figure. There are I/O blocks, which are designed and numbered according to function. For each module of logic level composition, there are CLB’s (Configurable Logic Blocks).

CLB does the logic operation given to the module. The inter connection between CLB and I/O blocks are made with the support of horizontal routing channels, vertical routing channels and PSM (Programmable Multiplexers).

The number of CLB it comprises simply chooses the difficulty of FPGA. The functionality of CLB’s and PSM are intended by VHDL or any other hardware descriptive language. After programming, CLB and PSM are sited on chip and linked with each other with routing channels.
fpga_introduction

Advantages

  • It needs very small time; starting from design process to functional chip.
  • No physical industrial steps are complicated in it.
  • The only difficulty is, it is expensive than other styles.

Gate Array Design

The gate array (GA) positions second after the FPGA, in terms of fast prototyping competence. While user program design is vital to the design application of the FPGA chip, metal mask design and processing is used for GA. Gate array implementation needs a two-step manufacturing process.

The first phase outcomes in an array of uncommitted transistors on each GA chip. These uncommitted chips can be stowed for later customization, which is finished by describing the metal interconnects between the transistors of the array. The patterning of metallic interconnects is done at the end of the chip fabrication process, so that the inversion time can still be short, a few days to a few weeks. The figure given beneath displays the basic processing steps for gate array implementation.
gate_array_design

Distinctive gate array platforms use committed areas called channels, for inter-cell routing between rows or columns of MOS transistors. They make simpler the interconnections. Interconnection designs that perform simple logic gates are kept in a library, which can then be used to modify rows of uncommitted transistors according to the net list.

In best of the current GAs, multiple metal layers are used for channel routing. With the use of numerous interconnected layers, the routing can be succeeded over the active cell areas; so that the routing channels can be detached as in Sea-of-Gates (SOG) chips. Now, the entire chip exterior is covered with uncommitted nMOS and pMOS transistors. The adjacent transistors can be modified using a metal mask to form basic logic gates.

For inter cell routing, specific uncommitted transistors need to be lost. This design style effects in more elasticity for interconnections and typically in a higher density. GA chip operation factor is dignified by the used chip area divided by the total chip area. It is higher than that of the FPGA and so is the chip speed.

Standard Cell Based Design

A standard cell based design needs progress of a full custom mask set. The standard cell is also identified as the polycell. In this method, all of the usually used logic cells are established, characterized and stored in a standard cell library.

A library may comprise a few hundred cells comprising inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches and Flip-flops. Each gate type can be applied in numerous versions to offer acceptable driving capability for different fan-outs. The inverter gate can have standard size, double size, and multiply size so that the chip designer can select the proper size to obtain high circuit speed and layout density.
Every cell is considered according to numerous different characterization categories, such as,

  • Delay time versus load capacitance
  • Circuit simulation model
  • Timing simulation model
  • Fault simulation model
  • Cell data for place-and-route

Mask data

For automatic placement of the cells and routing, every cell layout is designed with a fixed height, so that a amount of cells can be bounded side-by-side to form rows. The power and ground rails run parallel to the upper and lower boundaries of the cell. So that, nearby cells shares a common power bus and a common ground bus. The figure shown underneath is a floor plan for standard-cell based design.
standard_cell_based_design

Full Custom Design

In a full-custom design, the whole mask design is made new, without the use of any library. The growth cost of this design style is rising. Therefore, the idea of design recycle is pretty famous to decrease design cycle time and development cost.

The firmest full custom design can be the design of a memory cell, be it static or dynamic. For logic chip design, a good compromise can be gotten using an arrangement of altered design styles on the same chip, i.e. standard cells, data-path cells, and programmable logic arrays (PLAs).

Basically, the designer organizes the full custom layout, i.e. the geometry, orientation, and placement of each transistor. The design output is typically very low; classically a few tens of transistors per day, per designer. In digital CMOS VLSI, full-custom design is almost not used due to the high work cost. These design styles comprise the design of high-volume products such as memory chips, high-performance microprocessors and FPGA.


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