Combinational MOS Logic Circuits - VLSI Design

What is Combinational MOS Logic Circuits?

Combinational logic circuits or gates, which accomplish Boolean processes on numerous input variables and determine the outputs as Boolean functions of the inputs, are the simple building blocks of all digital systems. We will inspect modest circuit configurations such as two-input NAND and NOR gates and then enlarge our study to more general cases of multiple-input circuit structures.

Resulting, the CMOS logic circuits will be obtainable in a comparable fashion. We will stress the resemblances and alterations between the nMOS depletion-load logic and CMOS logic circuits and point out the benefits of CMOS gates with samples. In its most common form, a combinational logic circuit, or gate, performing a Boolean function can be signified as a multiple-input, single-output system, as depicted in the figure. Node voltages, referenced to the ground potential, signify all input variables. By means of positive logic agreement, the Boolean (or logic) value of "1" can be signified by a high voltage of VDD, and the Boolean (or logic) value of "0" can be signified by a low voltage of 0. The output node is loaded with a capacitance CL, which signifies the joint capacitances of the parasitic device in the circuit.

CMOS Logic Circuits

CMOS Two input NOR Gate

The circuit contains of a parallel-connected n-net and a series-connected balancing p-net. The input voltages VX and VY are applied to the gates of one nMOS and one pMOS transistor.

When either one or both efforts are high, i.e., when the n-net generates a leading path among the output node and the ground, the p-net is cut—off. If input voltages are low, i.e., the n-net is cut-off, then the p-net creates a conducting path between the output node and the supply voltage.
For any given input combination, the balancing circuit structure is such that the output is linked either to VDD or to ground via a low-resistance path and a DC current path among the VDD and ground is not recognized for any input mixtures. The output voltage of the CMOS, two did not input NOR gate will get a logic-low voltage of VOL = 0 and a logic-high voltage of VOH = VDD. The equation of the switching threshold voltage Vth is given by ${V}_{th}\left(NOR2\right)=\frac{{V}_{T,n}+\frac{1}{2}\sqrt{\frac{{k}_{p}}{{k}_{n}}\left({V}_{DD}-|{V}_{T,p}|\right)}}{1+\frac{1}{2}\sqrt{\frac{{k}_{p}}{{k}_{n}}}}$ 

Layout of CMOS 2-input NOR Gate The figure displays a example layout of CMOS 2-input NOR gate, using single-layer metal and single-layer polysilicon. The features of this layout are −

• Single vertical polylines for each input
• Single active shapes for N and P devices, respectively
• Metal buses running horizontal

The stick diagram for the CMOS N0R2 gate is presented in the figure given below; which resembles openly to the layout, but does not comprise W and L information. The diffusion areas are portrayed by rectangles, the metal associates and solid lines and circles, correspondingly represent contacts, and the crosshatched strips represent the polysilicon columns. Stick diagram is useful for planning optimum layout topology. CMOS Two-input NAND Gate

The circuit diagram of the two input CMOS NAND gate is given in the figure below. The source of process of the circuit is precise dual of the CMOS two input NOR operation. The n – net consisting of two succession connected nMOS transistor creates a leading path among the output node and the ground, if both input voltages are logic high. Both of the parallelly connected pMOS transistor in p-net will be off.

For all other input grouping, either one or both of the pMOS transistors will be turn ON, while p – net is cut off, therefore, making a current path among the output node and the power supply voltage. The switching threshold for this gate is obtained as -${V}_{th}\left(NAND2\right)=\frac{{V}_{T,n}+2\sqrt{\frac{{k}_{p}}{{k}_{n}}\left({V}_{DD}-|{V}_{T,p}|\right)}}{1+2\sqrt{\frac{{k}_{p}}{{k}_{n}}}}$ 

The types of this layout are as follows −

• Single polysilicon lines for inputs run perpendicularly across both N and P active regions.
• Single active shapes are used for building both nMOS devices and both pMOS devices.
• Power bussing is running horizontal across top and bottom of layout.
• Output wires runs horizontal for easy connection to neighboring circuit.

Complex Logic Circuits

NMOS Depletion Load Complex Logic Gate

To understand compound functions of numerous input variables, the simple circuit constructions and design values developed for NOR and NAND can be protracted to complex logic gates. The aptitude to understand complex logic functions, using a small number of transistors is one of the most good-looking features of nMOS and CMOS logic circuits. Think through the following Boolean function as an instance. $\overline{Z=P\left(S+T\right)+QR}$

The nMOS depletion-load difficult logic gate used to understand this function is shown in figure. In this figure, the left nMOS driver branch of three driver transistors is used to perform the logic function P (S + T), while the right-hand side branch performs the function QR. By linking the two outlets in parallel, and by insertion the load transistor among the output node and the supply voltage VDD, we get the given composite function. Each input variable is allocated to only one driver. Review of the circuit topology offers meek design values of the pull-down network −

• OR operations are performed by parallel-connected drivers.
• AND operations are performed by series-connected drivers.
• Inversion is provided by the nature of MOS circuit operation.

If all input variables are logic-high in the circuit understanding the function, the equivalent driver (W/L) ratio of the pull-down network consisting of five nMOS transistors is

$\frac{W}{L}=\frac{1}{\frac{1}{\left(W/L\right)Q}+\frac{1}{\left(W/L\right)R}}+\frac{1}{\frac{1}{\left(W/L\right)P}+\frac{1}{\left(W/L\right)S+\left(W/L\right)Q}}$

Complex CMOS Logic Gates

The understanding of the n-net, or pull-down network, is founded on the same elementary design values inspected for nMOS depletion-load complex logic gate. The pMOS pull-up network must be the dual network of the n-net.

It incomes all parallel associates in the nMOS network will resemble to a series connection in the pMOS network, and all sequence connection in the nMOS network agree to a parallel connection in the pMOS network. The figure shows a simple construction of the dual p-net (pull-up) graph from the n-net (pull-down) graph. Every driver transistor in the pull-down network is revealed by ai and each node is shown by a vertex in the pull-down graph. Then, a new vertex is formed inside each limited area in the pull graph, and adjacent vertices are linked by edges which cross each edge in the pull-down graph merely once. This new graph shows the pull-up network. Layout Technique using Euler Graph Method

The figure shows the CMOS application of a complex function and its stick diagram done with random gate ordering that gives a very non-optimum layout for the CMOS gate.

In this circumstance, the parting between the polysilicon columns must let diffusion-todiffusion separation in between. This surely eats a considerably amount of extra silicon area.  By means of the Euler path, we can achieve an ideal layout. The Euler path is distinct as an continuous path that traverses each edge (branch) of the graph precisely once. Find Euler path in both the pull-down tree graph and the pull-up tree graph with identical ordering of the inputs.

VLSI Design Topics