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UVM (Universal Verification Methodology) is a standardized methodology for verifying the both complex & simple digital design in simple way.
Here is the detailed connection between SV, UVM, OVM and other methodologies.
Only build phase is a top-down & other phases are bottom-up except run phase which is parallel. The build phase works top-down since the test bench hierarchy may be configure so we need to build the branches before leafs.
The connect phase is intended to be used for making TLM connections between components, which is why it occur after build phase. It work bottom-up so that its got the correct implementation all the way up the design hierarchy, if worked top-down this would be not possible.
Only run phase is a task (time consuming phase) & other phases are functions (non-blocking).
As previously said the run phase is implemented as task and remaining all are function. run phase will get executed from start of simulation to till the end of simulation. run phase is time consuming, where the test case is running.
UVM phases initiate by calling run test (“test1”) in top module. When run test() method call, it first create the object of test top & then call all phases.
In top module write run test(); i.e. Don't give anything in argument.
Then in command line: +UVM_TESTNAME=test name.
uvm_do perform the below steps:
While `uvm_rand_send perform all the above steps except create. User needs to create sequence / sequence item.
class uvm_sequence_item extends uvm_transaction
Uvm_sequence_item extended from uvm_transaction only, uvm_sequence_item class has more functionality to support sequence & sequencer features. Uvm_sequence_item provides the hooks for sequencer and sequence, So you can generate transaction by using sequence and sequencer , and uvm_transaction provide only basic methods like do print and do record etc .
UVM is a methodology based on Systemverilog language and is not a language on its own. It is a standardized methodology that defines several best practices in verification to enable efficiency in terms of reuse and is also currently part of IEEE 1800.2 working group.
Some of the benefits of using UVM are:
In addition to the predefined phases available in uvm , the user has the option to add his own phase to a component. This is typically done by extending the uvm_phase class the constructor needs to call super. new which has three arguments.
The call task or call_func and get_type_name need to be implemented to complete the addition of new phase.
Below is a simple example
Class custom phase extends uvm_phase;
Function new ();
Super. New (“custom”, 1, 1);
Task call task (uvm_component parent);
If ( $cast(comp, parent) )
comp.custom phase ();
Virtual function string get_type_name ();
In a verification context, a register model (or register abstraction layer) is a set of classes that model the memory mapped behavior of registers and memories in the DUST in order to facilitate stimulus generation and functional checking (and optionally some aspects of functional coverage). The UVM provides a set of base classes that can be extended to implement comprehensive register modeling capabilities.
We all know about new () method that is use to allocate memory to an object instance. In UVM (and OVM), the create () method causes an object instance to be created from the factory. This allows you to use factory overrides to replace the desired object with an object of a different type without having to recode.
Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method write implemented in another component, specifically a subscriber.
port, export, and imp classes used for transaction analysis.
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.
Receives all transactions broadcasted by a uvm_analysis_port.
Exports a lower-level uvm_analysis_imp to its parent.
In simpler words TLM FIFO is a FIFO between two UVM components, preferably between Monitor and Scoreboard. Monitor keep on sending the DATA, which will be stored in TLM FIFO, and Scoreboard can get data from TLM FIFO whenever needed.
// create a FIFO with depth 4
tlm_fifo = new ("uvm tlm_fifo", this, 4);
Start item starts the sequence
Virtual task start item (uvm_sequence_item item,
int set priority = -1,
Uvm_sequencer_base sequencer = null )
Start item and finish item together will initiate operation of a sequence item. If the item has not already been initialized using create item, then it will be initialized here to use the default sequencer specified by m_sequencer.
Raising an objection: phase.raise_objection (this);
Dropping an objection: phase.drop_objection (this);
M_sequencer is the default handle for uvm_vitual_sequencer and m_sequencer is the hook up for child sequencer.
M_sequencer is the generic uvm_sequencer pointer. It will always exist for the uvm_sequencer and is initialized when the sequence is started.
P_sequencer is a typed-specific sequencer pointer, created by registering the sequence to the sequencer using macros (`uvm_declare_p_sequencer) . Being type specific, you will be able to access anything added to the sequencer (i.e. pointers to other sequencers, etc.). M_sequencer will not exist if we have not registered the sequence with the `uvm_declare_p_sequencer macros.
The drawback of m_sequencer is that once the m_sequencer is defined, one cannot run the sequence on any other sequencer type.
An agent is a collection of a sequencer, a driver and a monitor.
In active mode, the sequencer and the driver are constructed and stimulus is generated by sequences sending sequence items to the driver through the sequencer. At the same time the monitor assembles pin level activity into analysis transactions.
In passive mode, only the monitor is constructed and it performs the same function as in an active agent. Therefore, your passive agent has no need for a sequencer. You can set up the monitor using a configuration object.
The built-in copy () method executes the __m_uvm_field_automation() method with the required copy code as defined by the field macros (if used) and then calls the built-in do copy() virtual function. The built-in do copy () virtual function, as defined in the uvm_object base class, is also an empty method, so if field macros are used to define the fields of the transaction, the built-in copy() method will be populated with the proper code to copy the transaction fields from the field macro definitions and then it will execute the empty do copy() method, which will perform no additional activity.
The copy() method can be used as needed in the UVM test bench. One common place where the copy() method is used is to copy the sampled transaction and pass it into a sb_calc_exp() (scoreboard calculate expected) external function that is frequently used by the scoreboard predictor.
The clone () method calls the create () method (constructs an object of the same type) and then calls the copy() method. It is a one-step command to create and copy an existing object to a new object handle.
UCM Factory is used to manufacture (create) UVM objects and components. Apart from creating the UVM objects and components the factory concept essentially means that you can modify or substitute the nature of the components created by the factory without making changes to the test bench.
For example, if you have written two driver classes, and the environment uses only one of them. By registering both the drivers with the factory, you can ask the factory to substitute the existing driver in environment with the other type. The code needed to achieve this is minimal, and can be written in the test.
There are two types of sequencers:
uvm_sequencer #(REQ, RSP) :
When the driver initiates new requests for sequences, the sequencer selects a sequence from a list of available sequences to produce and deliver the next item to execute. In order to do this, this type of sequencer is usually connected to a driver uvm_driver #(REQ, RSP).
uvm_push_sequencer #(REQ, RSP) :
The sequencer pushes new sequence items to the driver, but the driver has the ability to block the item flow when it’s not ready to accept any new transactions. This type of sequencer is connected to a driver of type uvm_push_driver # (REQ, RSP).
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