The information between the I/O and the peripheral devices and between the shared memory is passed smoothly and fast by using an efficient system that interconnects the multiprocessors.
Parallel processing needs the use of efficient system interconnects for fast communication among the Input/Output and peripheral devices, multiprocessors and shared memory.
There are main types of multiprocessor system interconnects in parallel algorithm. They are -
A number of signals, control and power lines constitute together forming a Bus. These buses are enabled as connection between different systems and sub-systems. The buses are connected with different systems and sub-systems of the computer forming a hierarchy and known as hierarchical bus systems. The different types of the interconnection functions are performed by using variety of buses such as local buses, backplane buses and I/O buses.
The buses which are used for the printed-circuit boards are considered as local buses. The printed circuit board that facilitates in plugging many functional boards is known as backplane bus. The buses that facilitate in connecting the computer system with the I/O devices are referred as I/O buses.
Crossbar networks are widely used by the medium sized or small systems. The network system of both crossbar switch and multiport memory is considered to be single-stage. The single-stage networks are built at low cost.
For developing few connections, multiple passes are required, and thus the single-stage network does not serve the purpose. The switch boxes for the multistage networks are more and hence can be useful in these cases. Any of the input can be connected to any of the output by using these networks.
The network built in such a way that the processing elements are positioned at one end of the network and memory elements on the other end. And both of them are connected using the switching elements. These high-speed computer networks are known as multistage networks or multistage interconnection networks.
Some of the huge multiprocessor systems are developed by using these networks. Examples of these networks include Omega Network, Butterfly Network.
The model of a multicomputer is depicted below. A multicomputer is usually distributed memory MIMD architecture.
Multicomputers are used for exchanging the data. These computer use packet switching method. A private memory is allocated to each of the processors which cannot be accessed by other processors. This restricts the free flow of communication and the communication can be made smooth by using communication primitives in the codes written.
The main disadvantage of the multicomputers is absence of globally accessible memory. Parallel architecture provides two different schemes to overcome this drawback.
A huge globally addressed shared memory is assumed by the application programmer. These are then transformed as the concepts of message-passing.
Virtual shared memory facilitates in developing the operating system in the form of virtual memory system, which runs on the VSM and is an hardware implementation. It is assumed by the operating system that the operating system is run on the shared memory machine.
The operating system enables SVM by aiding the hardware assistance from the processor Memory Management Unit (MMU) as it is software implementation. The memory pages of the operating system are shared by SVM.
To identify whether the memory page constitute a part of the local memory, MMU is used for addressing a specific memory location. The operating system swap from the disk, in the absence of page in the local memory. In such instances, SVM facilitates the operating system to bring back the page from the remote node.
The three different generations of multicomputers are as follows -
Always the low-cost processors are selected for designing the processor technology. The off-the-shelf microprocessors are widely used for developing parallel computers. Multi computer always preferred distributed memory upon shared memory. A local memory unit was fixed to each of the processors.
Direct networks which enable point-to-point communication were used for passing the messages. Mostly the operations such as MIMD, MPMD, and SMPD were used for designing multicomputers.
Globally shared virtual memory was used by the next generation computers. These types of computers are widely used and are still in use at present. The usage of the high versions of the processors such as i386, i860, has enabled to the development of the second generation computers.
It is considered that the next generation computers use VLSI nodes with each of the node have a single chip with 14-MIPS processor, 20-Mbytes/s routing channels and 16 Kbytes of RAM.
Earlier hypercube multicomputers were used which were delegating the functions to the host computer and hence the bandwidth of the I/O was limited. These computers were not much accepted for use considering the expected high throughput and solving of the large-scale problems. To overcome this drawback, parallel architecture designed Intel Paragon System. This system transformed the multicomputer into an application server which can be accessed in any network environment.
An intense support from the hardware and software are essential for passing of the message in any multicomputer network. Some of the mechanisms for passing the message in multicomputers are as follows -
The units for transmission of information used by the store and forward routing mechanism is packets. The units for transmission of information used by the warmhole routing mechanism is flits (which are the sub-divisions of packets). The size of the network influence the length of the flit and the network implementation influence the length of the packet.
The units for transmission of information used by the store and forward routing mechanism is packets. The intermediate nodes enable to transfer the packet from the source node to the destination node where a buffer packet is used by each of the nodes. The distance between source and destination is determined in terms of latency.
Routers enable to transfer from the source node to the destination node. Flits of a particular packet are transferred in together without separation. The path of the packet is only known to the header flit.
The logical link that exists between any two nodes is referred as virtual channel. The source and the destination nodes always carry a flit buffer which enables development of a physical channel between the source and the destination. For a particular pair, the assigned physical channel enables to form a virtual channel between the source buffer and the receiver buffer.
Deadlock occurs when none of the channels are free and all the channels are filled with messages. The deadlock avoidance scheme is designed by the parallel architecture to overcome the instances of deadlock.
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