AMBA AHB Interview Questions & Answers

AMBA AHB Interview Questions

Are you an engineering graduate with good command on technical skills? Are you a person willing to work in different environment then log on to AMBA AHB Advanced Microcontroller Bus Architecture is an open standard, on chip interconnect specification for the connection and management bid functional blocks in system on chip (SoC) designs. It facilities development of multiprocessor designs with large numbers of controllers and peripherals. AHB is Advanced High PerformanceBus and is part of AMBA, transfer can start with the bus master, by asserting a request signal to the arbiter. Then the arbiter when the master will be granted to use the bus. A granted Master bus starts the transfer with address and control signal. So track your future as Soc Verification Engineer, Digital Verification Engineer, Senior Silicon Engineer, lead IP Engineer and so on by looking into AMBA AHB job interview question and answers given.

AMBA AHB Interview Questions And Answers

AMBA AHB Interview Questions
    1. Question 1. When Should A Master Assert And Deassert The Block Signal For A Locked Transfer?

      Answer :

      The GLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at the start of the address phase.

      The master should deassert the HLOCK signal when the address phase of the last transfer in the locked sequence has started.

    2. Question 2. Can An Arbiter Be Designed To Always Allow Bursts To Complete?

      Answer :

      A SPLIT, RETRY or ERROR response from a slave can always cause a burst to be early terminated. This is outwith the control of the Arbiter and so must be supported.

      Undefined length INCR bursts cannot have their end point predicted, so there is no efficient way that an Arbiter design can allow the burst to complete before granting another master. INCR bursts must be arbitrated ona cycle by cycle basis.

      Defined length INCRx and WRAPx bursts can have their beats counted, and so allowed to complete by the Arbiter. However because of the AHB arbitration synchronous timing, there is no way to avoid possibly terminating a burst immediately after the first transfer of the burst has been indicated.

      The Arbiter only knows that a defined length burst is in progress by sampling the HBURST bus. However the first point at which HBURST can be sampled is after the first clock cycle of the first burst beat, by which time the Arbiter may already have decided to grant another master and will have changed the HGRANT outputs accordingly. Only a combinatorial path from HBURST to HGRANT would allow the burst to be detected in time to avoid early termination in this scenario, but combinatorial paths in the AHB bus are not allowed.

    3. Question 3. Why Is Haddr Sometimes Shown As An Input To The Arbiter?

      Answer :

      The address bus, HADDR, is not required as an input to the arbiter but in some system designs it may be useful to use the address bus to determine a good point to change over between bus masters. For example, the arbiter could be designed to change bus ownership when a burst of transfers reaches a quad word boundary.

    4. Question 4. When Can The Hgrant Signal Change?

      Answer :

      The GRANT signal can change in any cycle and the following cases are possible:

      • It is possible that the HGRANT signal may be asserted and then removed before the current transfer completes. This is acceptable because the HGRANT signal is only sampled by masters when HREADY is high.
      • A master can be granted the bus without requesting it.
      • The above point also means that it is possible to be granted the bus in the same cycle that it is requested. This can occur if the master is coincidentally granted the bus in the same cycle that it requests it.

    5. Question 5. What Is The Relationship Between The Hlock Signal And The Hmastlock Signal?

      Answer :

      At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of the master that is about to start driving the address bus and if HLOCK is asserted at this point then HMASTLOCK will be asserted by the arbiter for the duration of the address phase of the transfer.

    6. Question 6. When Should A Master Deassert Its Hbusreq Signal?

      Answer :

      For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it has started the address phase of the last transfer in the burst. This will mean that if the penultimate transfer in the burst is zero wait state then the master may be granted the bus for an additional transfer at the end of an undefined length burst.

      For a defined length burst the master can deassert the HBUSREQ signal once the master has been granted the bus for the first transfer. This can be done because the arbiter is able to count the transfers in the burst and keep the master granted until the burst completes.

      However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has been completed.

    7. Question 7. When Will The Arbiter Grant Another Master After A Locked Transfer?

      Answer :

      The arbiter will always grant the master an extra transfer at the end of a locked sequence, so the master is guaranteed to perform one transfer with the HMASTLOCK signal low at the end of the locked sequence. This coincides with the data phase of the last transfer in the locked sequence.

      During this time the arbiter can change the HGRANT signals to a new bus master, but if the data phase of the last locked transfer receives either a SPLIT or RETRY response then the arbiter will drive the HGRANT signals to ensure that either the master performing the locked sequence remains granted on the bus for a RETRY response, or the Dummy master is granted the bus for the SPLIT response.

    8. Question 8. Can A Master Deassert Hlock During A Burst?

      Answer :

      The AHB specification requires that all address phase timed control signals (other than HADDR and HTRANS) remain constant for the duration of a burst.

      Although HLOCK is not an address phase timed signal, it does directly control the HMASTLOCK signal which is address phase timed.

      Therefore HLOCK must remain high for the duration of a burst, and can only be deasserted such that the following HMASTLOCK signal changes after the final address phase of the burst.

    9. Question 9. If A Master Is Currently Granted The Bus By Default, How Many Cycles Before Starting An Non-idle Transfer Does It Have To Assert Hbusreq?

      Answer :

      None. It can start a non IDLE transfer immediately.

    10. Question 10. Can A Master Perform Transfers Other Than Idle When The Bus Was Granted To It, But Not Requested By The Master?

      Answer :

      Yes. A master can perform transfers other than IDLE when it had not requested the bus. Please note that in this case it is still recommended that the master asserts its request signal so that the arbiter does not change ownership of the bus to a lower priority master while the transfers are in progress.

    11. Question 11. The Specification Recommends That Only 16 Wait States Are Used. What Should You Do If More Than 16 Cycles Are Needed?

      Answer :

      For some slaves it is acceptable to insert more than 16 wait states. For example, a serial boot ROM which is only ever accessed at initial power up could insert a larger number of wait states and it would not affect the calculation of the system performance and latency once system power up has been completed.

      For other slaves a number of options exist. A SPLIT or RETRY response could be used to indicate that the slave is not yet able to perform the requested data transfer, or the slave could be accessed either in response to interrupts or after polling a status register, in either case indicating that the slave is now able to respond in an acceptable number of cycles.

    12. Question 12. Why Is A Burst Not Allowed To Cross A 1 Kilobyte Boundary?

      Answer :

      If an AHB slave samples HSELx at the start of a burst transaction, it knows it will be selected for the duration of the burst. Also, a slave which is not selected at the start of a burst will know that it will not become selected until a new burst is started.

      1 kilobyte is the smallest area an AHB slave may occupy in the memory map.

      Therefore, if a burst did cross a 1 kilobyte boundary, the access could start accessing one slave at the beginning of the burst and then switch to another on the boundary, which must not happen for the above reason.

      The 1 kilobyte boundary has been chosen as it is large enough to allow reasonable length bursts, but small enough that peripherals can be aligned to the 1 kilobyte boundary without using up too much of the available memory map.

    13. Question 13. Can An Ahb Master Be Connected Directly To An Ahb Slave?

      Answer :

      Any slave which does not use SPLIT responses can be connected directly to an AHB master. If the slave does use SPLIT responses then a simplified version of the arbiter is also required.

      If an AHB master is connected directly to an AHB slave it is important to ensure that the slave drives HREADY high during reset and that the select signal HSEL for the slave is tied permanently high.

    14. Question 14. What Is The State Of The Ahb Signals During Reset?

      Answer :

      The specification states that during reset the bus signals should be at valid levels. This simply means that the signals should be logic '0' or '1', but not Hi-Z. The actual logic levels driven are left up to the designer. HTRANS is the only signal specified during reset, with a mandatory value of IDLE.

      It is important that ALREADY is high during reset. If all slaves in the system drive HARDY high during reset then this will ensure that this is the case. However, if slaves are used which do not drive HREADY high during reset it should be ensured that a slave which does drive HREADY high is selected at reset.

    15. Question 15. Can A Busy Transfer Occur At The End Of A Burst?

      Answer :

      A BUSY transfer can only occur at the end of an undefined length burst (INCR). A BUSY transfer cannot occur at the end of a fixed length burst (SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).

    16. Question 16. What Is A Default Slave?

      Answer :

      If the memory map of a system does not define the full 4 gigabyte address space then a default slave is required, which is selected when an access is attempted to the empty areas of the memory map. The default slave should use an OKAY response for IDLE/BUSY transfers and an ERROR response sequence for NONSEQ/SEQ transfers.

    17. Question 17. Is A Default Slave Really Necessary?

      Answer :

      If the entire 4 gigabyte address space is defined then a default slave is not required. If, however, there are undefined areas in the memory map then it is important to ensure that a spurious access to a non-existent address location will not lock up the system. The functionality of the default slave is extremely simple and it will often make sense to implement this within the decoder.

    18. Question 18. Is A Dummy Master Really Necessary?

      Answer :

      A dummy master is necessary in any system which has a slave that can give SPLIT transfer responses. The dummy master is required so that something can be granted the bus if all the other masters have received a SPLIT response.

      No logic is required for the dummy master and it can be implemented by simply tying off the inputs to the master address/control multiplexer for the dummy master position. The requirements for a dummy master are that HTRANS is driven to IDLE, GLOCK is driven low, and all other master outputs are driven to legal values.

    19. Question 19. Is It Specified That Hprot, Hsize And Hwrite Remain Constant Throughout A Burst?

      Answer :

      Yes, the control signals must remain constant throughout the duration of a burst.

    20. Question 20. What Default State Should Be Used For The Hready And Hresp Outputs From A Slave?

      Answer :

      It is recommended that the default value for HREADY is high and the default value for HRESP is OKAY. This combination ensures that the slave will respond correctly to IDLE transfers to the slave, even if the slave is in some form of power saving mode.

    21. Question 21. Is Hready An Input Or An Output From Slaves?

      Answer :

      An AHB slave must have the HREADY signal as both an input and an output.

      HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer.

      HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.

      Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input.

    22. Question 22. How Many Masters Can There Be In An Ahb System?

      Answer :

      The AHB specification caters for up to 16 masters. However, allowing for a dummy bus master means the maximum number of real bus masters is actually 15. By convention bus master number 0 is allocated to the dummy bus master.

    23. Question 23. Can A Master Change The Address/control Signals During A Waited Transfer?

      Answer :

      Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low.

      However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

    24. Question 24. When A Master Rebuilds A Burst Which Has Been Terminated Early Are There Any Limitations On How It Rebuilds The Burst?

      Answer :

      The only limitation is that the master uses legal burst combinations to rebuild the burst. For example, if a master was performing an 8 beat burst, but had only completed 3 transfers before losing control of the bus, then the remaining 5 transfers could be performed either by using a 1 beat SINGLE burst followed by a 4 beat INCR burst, or it could be performed using a 5 beat undefined length INCR burst.

      For simplicity it is recommended that masters use INCR bursts to rebuild the remaining transfers.

    25. Question 25. What Is The Recommended Default Value For Hprot?

      Answer :

      Many bus masters will not be able to generate accurate protection information and for these bus masters it is recommended that the HPROT encoding shows, Non-cacheable, Non-bufferable, Privileged, Data Accesses which corresponds to HPROT[3:0] = 4'b0011.

    26. Question 26. Do All Slaves Have To Support The Busy Transfer Type?

      Answer :

      Yes. All slaves must support the BUSY transfer type to ensure they are compatible with any bus master.

    27. Question 27. What System Support Is Required If A Slave Can Be Powered Down Or Have Its Clock Stopped?

      Answer :

      If a slave access is attempted while that slave is in a power down state or has had its clock stopped, you must ensure that an access will cause the power/clock to be restored, or else configure the AHB decoder up to redirect any such accesses to the dummy slave so that the system does not hang forever when an access to the device is made when it is disabled.

      Redirecting the access in this way will ensure that random "IDLE" addresses are treated with the HREADY high and HRESP=OKAY default response, but real accesses (NONSEQ or SEQ) will be detected with an ERROR response.

    28. Question 28. When Can Early Burst Termination Occur?

      Answer :

      Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note however that a master cannot decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses.

      All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.

    29. Question 29. Does The Address Have To Be Aligned, Even For Idle Transfers?

      Answer :

      Yes. The address should be aligned according to the transfer size (HSIZE) even for IDLE transfers. This will prevent spurious warnings from bus monitors used during simulation.

    30. Question 30. What Is The Difference Between A Dummy Bus Master And A Default Bus Master?

      Answer :

      The term default bus master is used to describe the master that is granted when none of the masters in the system are requesting access to the bus. Usually the bus master which is most likely to request the bus is made the default master.

      The dummy bus master is a master which only performs IDLE transfers. It is required in a system so the arbiter can grant a master which is guaranteed not to perform any real transfers. The two cases when the arbiter would need to do this are when a SPLIT response is given to a locked transfer and when a SPLIT response is given and all other masters have already been SPLIT.

    31. Question 31. Is It Legal For A Master To Change Haddr When A Transfer Is Extended?

      Answer :

      If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY transfer then it cannot change the address during an extended transfer(when HREADY is low) unless it receives an ERROR, RETRY or SPLIT response.

      If the master is indicating that it wants to do an IDLE transfer then it may change the address.

    32. Question 32. Can Htrans Change Whilst Hready Is Low?

      Answer :

      In general, an AHB master should not change control signals whilst HREADY is low.

      However it is allowable to change HTRANS in the following conditions:

      The AHB master is performing internal operations and has not yet committed to a bus transfer. However during the AHB wait states (HREADY low) the master may determine that a bus transfer is required and change
      HTRANS on the next cycle to NONSEQ.
      HTRANS is being used to give the master time to complete internal operations, which may be entirely independent of HREADY (i.e. wait states on the AHB). Therefore HTRANS can change on the next cycle to any legal value, i.e. SEQ if the burst is to continue, IDLE if the burst has completed, NONSEQ if a separate burst is to begin.


      As stated in the AHB specification, a master must assert IDLE on HTRANS during the second cycle of the two-cycle SPLIT or RETRY slave response so HTRANS will change value from the first cycle to the second cycle of the response.
      The master is permitted to change HTRANS in reaction to an ERROR response in the same way as in reaction to a SPLIT/RETRY response and cancel any further beats in the current burst (even if HBURST is indicating a defined-length burst). In this case HTRANS changes to IDLE on the second cycle of the response. Alternatively, the master is permitted to continue with the current transfers

    33. Question 33. What Are The Different Bursts Used For?

      Answer :

      Typically a master would use wrapping bursts for cache line fills where the master wants to access the data it requires first and then it completes the burst to fetch the remaining data it requires for the cache line fill.

      Incrementing bursts are used by masters, such as DMA controllers, that are filling a buffer in memory which may not be aligned to a particular address boundary.

    34. Question 34. How Should Ahb To Apb Bridges Handle Accesses That Are Not 32-bits?

      Answer :

      The bridge should simply pass the entire 32-bit data bus through the bridge. Please note that when transfers less than 32-bits are performed to an APB slave it is important to ensure that the peripheral is located on the appropriate bits of the APB data bus.

    35. Question 35. What Value Should Be Used For Htrans When An Ahb Master Gets A Retry Response From A Slave In The Middle Of Burst?

      Answer :

      Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it may also be necessary to adjust the HBURST information (usually just to indicate INCR).

    36. Question 36. What Address Should Be On The Bus During The Idle Cycle After A Split Or Retry?

      Answer :

      It does not matter what address is driven onto the bus during this cycle.

      The slave selected by the driven address should not take any action and must respond with a zero wait state OKAY response.

      In many cases it will be simpler for the master to leave the address unaltered during this cycle, so that it remains at the address of the next transfer that the master wishes to perform and only in the following cycle does the master return the address to that of the transfer that must be repeated because of the SPLIT or RETRY response.

      In some designs it may be possible for the master to return the address to that required to repeat the previous transfer during the IDLE cycle and this behaviour is also perfectly acceptable.

    37. Question 37. Do All Masters Have To Support Split And Retry?

      Answer :

      Yes. All masters must support SPLIT and RETRY responses to ensure they are compatible with any bus slave. A master will handle both SPLIT and RETRY responses in an identical manner.

    38. Question 38. Can A Split Or Retry Response Be Given At Any Point During A Burst?

      Answer :

      Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any transfer during a burst. The slave is not restricted to only giving these responses to the first transfer.

    39. Question 39. Will A Master Always Lose The Bus After A Split Response?

      Answer :

      Yes. A slave must not assert the relevant bit of the SPLIT bus in the same cycle that it gives the SPLIT response and therefore the master will always lose the bus.

    40. Question 40. Can A Slave Assert Hsplitx In The Same Cycle That It Gives A Split Response?

      Answer :

      No. The specification requires that HSPLITx can only be asserted after the slave has given a SPLIT response.

    41. Question 41. Do All Slaves Have To Support The Split And Retry Responses?

      Answer :

      No. A slave is only required to support the response types that it needs to use. For example, a simple on-chip memory block which can respond to all transfers in just a few wait states does not need to use either the SPLIT or RETRY responses.

    42. Question 42. Can A Slave Use Both Split And Retry Responses?

      Answer :

      Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT response should be used by any slave that may be accessed by many different masters at the same time. The RETRY response is intended to be used by peripherals that are only accessed by one bus master.

    43. Question 43. What Is The Difference Between Split And Retry Responses?

      Answer :

      Both the Split and Retry responses are used by slaves which require a large number of cycles to complete a transfer. These responses allow a data phase transfer to appear completed to avoid stalling the bus, but at the same time indicate that the transfer should be re-attempted when the master is next granted the bus.

      The difference between them is that a SPLIT response tells the Arbiter to give priority to all other masters until the SPLIT transfer can be completed (effectively ignoring all further requests from this master until the SPLIT slave indicates it can complete the SPLIT transfer), whereas the RETRY response only tells the Arbiter to give priority to higher priority masters.

      A SPLIT response is more complicated to implement than a RETRY, but has the advantage that it allows the maximum efficiency to be made of the bus bandwidth.

      The master behaviour is identical to both SPLIT and RETRY responses, the master has to cancel the next access and re-attempt the current failed access.

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